timing
Clock Skew and Its Effect on Timing
TL;DR: Clock skew is the difference between when a clock edge arrives at one flip-flop and when it arrives at the next. Positive skew (the receive flip-flop sees the edge...
Tag
timing
A collection of 3 posts
combinational-logic
Static vs Dynamic Hazards in Combinational Logic
TL;DR: A static hazard is a momentary glitch on an output that should have stayed constant; a dynamic hazard is multiple transitions on an output that should have changed exactly...
clock-signal
The Clock Pulse: Why Computers Need a Heartbeat
TL;DR: A clock signal is a periodic square wave (typically 50% duty cycle) that synchronizes every flip-flop and pipeline stage in a synchronous digital system. Modern CPUs derive multi-GHz clocks...