Multiplexer Explained: The Relay Circuit That Chooses Between Signals

In the previous post, we completed the full set of two-input logic gates — AND, OR, NAND, NOR, XOR, XNOR — each one a different question about its inputs. Every gate in that tour did the same kind of work: it computed. It took data in, applied a rule, and put a result out. Every input was the same species of thing: a bit to be reasoned about.

Today something fundamentally new enters the circuit. We still have two data inputs and one output. But now we add a third input that plays an entirely different role. It doesn’t get computed on. It chooses which of the other inputs reaches the output. It is a select signal — a control bit that steers data rather than participating in it.

That distinction — data versus control — is not a subtle naming convention. It is one of the most important ideas in all of computing, and a relay circuit built from first principles is the best possible place to see it born.

What a multiplexer does, from scratch

A 2-to-1 multiplexer (commonly written 2:1 MUX) has three inputs and one output:

• A — first data input
• B — second data input
• S — select (control) input
• Out — the output

The operating rule is stark in its simplicity: when S = 0, the output follows A and ignores B entirely. When S = 1, the output follows B and ignores A entirely.

In Boolean algebra:

$\text{Out} = (\overline{S} \wedge A) \vee (S \wedge B)$

Read this as two separately gated paths joined at the output. When S is 0, the term $\overline{S}$ is 1 and the term $S$ is 0 — the A path is open, the B path is sealed shut. When S is 1, the situation reverses: the B path opens, the A path closes. The two gating halves can never both be active simultaneously; they are mutually exclusive by the algebra of S and its complement.

In relays, the construction mirrors that algebra directly. One relay inverts S to produce $\overline{S}$. Two relay contacts gate each data path — one path controlled by $\overline{S}$ and A in series, the other by S and B in series. The two paths share the output in parallel, exactly as the OR expression says. The physics enacts the formula: only the currently selected path can carry current.

The word “multiplex” and why it exists

The word comes from Latin multiplex — “many-fold,” “composed of many parts.” It entered electrical engineering long before anyone had designed a logic gate, because the most expensive object in 19th-century telecommunications was wire.

Stringing telegraph cable across a continent cost a fortune in copper, labor, and surveyed right-of-way. Every mile of wire was a capital investment. Once you had it, you desperately wanted it to carry more than one message at a time. Could the same copper hold two conversations — or four — simultaneously?

Thomas Edison answered that challenge in 1874 with the quadruplex telegraph: a system that sent four independent messages over a single wire at once, encoding them as different combinations of electrical amplitude and polarity. Western Union paid Edison $10,000 for the invention and immediately quadrupled the message capacity of their existing network without laying a single new mile of cable. The word multiplex entered technical English to describe exactly this: one medium, many independent channels, a control mechanism to keep them sorted.

Telephone engineers extended the idea in two directions. Frequency-division multiplexing (FDM), which underpinned long-distance telephone networks from the 1910s onward, assigned each conversation its own narrow band of frequencies, stacked those bands like layers in a sandwich, and sent them together down a shared cable. At the far end, banks of tuned filters separated the layers — the filter’s resonant frequency was the “selector” that picked out one conversation from the stream.

Time-division multiplexing (TDM), which came to dominate digital telephony in the 20th century, worked differently. It gave each conversation the full wire, but only for a fraction of a second at a time, cycling through all conversations so rapidly that none noticed the interruption. A Bell System T1 line carrying 24 simultaneous voice channels cycled its selector 8,000 times per second — the wire was doing 24 things “at once” because a control signal was choosing, relentlessly, which conversation owned the channel at each moment.

Same name, same underlying logic: a control signal selects which data source gets the channel right now. Edison’s polarity switch, the FDM filter bank, the TDM frame clock — each is a select line, applied at a different scale and speed. The relay circuit below makes that selection visible down to the contact level.

The truth table: S routes the output

Eight rows capture all possible input combinations — the four pairings of A and B, each tested under both S = 0 and S = 1:

Stare at the two halves of that table separately. The top four rows (S = 0): Out is always identical to A. B is present in the table, but it contributes nothing — its column could be all zeros or all ones and the output would not change. The bottom four rows (S = 1): Out is always identical to B. A is now the irrelevant column.

The “unchosen” input is not merely outweighed or overridden. It is completely suppressed — invisible to the output. That suppression is what makes S a fundamentally different kind of signal from A and B. A and B are data: values that might or might not get through. S is control: an instruction that determines which data exists, as far as the output is concerned.

In every gate from the previous eleven posts, toggling any input could potentially affect the output. In a multiplexer, toggling the unchosen input cannot affect the output — guaranteed, unconditionally, by the circuit’s structure. That guarantee is new. It is the beginning of directed data flow.

Try it yourself — steer the signal

Below is a live 2-to-1 multiplexer built from relays in the DigiSim simulator — a genuine DC circuit, not an animation. Three switches: A, B, and S. One output lamp.

Three specific things to try:

1. Watch S act as a gatekeeper, not a data source. Set A = 1 and B = 0, then flip S back and forth. The output follows A when S = 0 and extinguishes when S = 1 — even though you never touched A or B. S alone rewired which data path is active. That is control.

2. Verify the suppression. Set S = 0. Now toggle B all the way on, all the way off, on again, off again. The output lamp doesn’t move. From the output’s perspective, B does not exist while S = 0. Now flip S = 1 and repeat the experiment with A — same result, same silence. Listen to the relay clicks as you flip S; that is the sound of a routing decision, not a logic operation.

3. Compare to the gates from earlier posts. In every prior circuit in this series, flipping any input might change the output. In this circuit, flipping the unchosen input cannot. That structural immunity is the difference between an input participating in a computation and an input waiting to be selected. The multiplexer is the first circuit here where the inputs have distinct jobs.

Why the data/control distinction is the whole idea

The 2-to-1 MUX might look like a modest extension — three inputs instead of two. But the conceptual distance is larger than it first appears.

In a logic gate, all inputs are peers: AND asks “are they both true?”, XOR asks “are they different?” The computation spans all inputs equally. In a multiplexer, inputs have roles. A and B are things being processed; S is an instruction about what to do with them. This separation of data and control is not a feature — it is the architectural principle behind every programmable machine ever built.

When a CPU fetches an instruction — ADD, MOVE, COMPARE, JUMP — what it is doing, at root, is exactly what S does, at massive scale. The instruction’s opcode bits fan out across the data path as select signals: this register feeds this functional unit, this bus connects to that buffer, this path opens and that one closes. The instruction is a vector of control bits that routes data through the machine for one operation, then a new instruction routes it differently for the next.

Register files — the small, fast memories that processors use to hold operands during computation — are banks of multiplexers. A three-bit address line (S2, S1, S0) selects among eight data sources, routing exactly one register’s value onto the data bus while suppressing the other seven. The circuit you just played with is the primitive cell of that structure: one selector bit, two data sources, one routed output.

Instruction decoding, the stage of a CPU pipeline that reads an opcode and decides which functional units activate, is logically a cascade of demultiplexers (the inverse of a MUX) feeding into MUX trees on the data path. Understanding the multiplexer is understanding the architectural atom behind all of it.

George Boole gave us the algebra of AND, OR, and NOT. Claude Shannon showed in his 1937 master’s thesis how to wire that algebra into relay networks. What the multiplexer adds to both is the concept of directed flow: not just “is this condition true?” but “given this condition, which path does the data take?” It is the first moment in this series where the circuit has something that feels like a decision embedded in its structure rather than a calculation. And it arrives, as so many computing ideas do, by solving an older, cheaper, more practical problem: how to send four telegraph messages down one wire.

What you just learned — and what’s next

In this post:

• A 2-to-1 multiplexer has two data inputs (A, B), one select input (S), and one output: when S = 0, Out = A; when S = 1, Out = B.
• The Boolean expression is $\text{Out} = (\overline{S} \wedge A) \vee (S \wedge B)$ — two AND-gated paths joined by OR, the select line opening exactly one at a time.
• The data vs. control distinction is the key new idea: S is not computed on, it steers what gets computed. The unchosen input is completely suppressed.
• Multiplexing in communications — from Edison’s 1874 quadruplex telegraph through FDM and TDM telephone networks — was driven by the identical underlying concept: a control signal selects which data source owns the channel.
• In real CPUs, MUX trees implement register selection, bus routing, and instruction decoding — the same pattern, scaled up from one select bit to many.

In Post 13, we turn from routing to arithmetic. We’ll build the half adder: two relay gates — one XOR and one AND — that add two single-bit numbers and produce both a sum and a carry. For the first time in this series, the circuit won’t just route or compare; it will count. One step from counting to adding any numbers you like.

Every circuit in this series lives in the DigiSim Relay Lab.