d-flip-flop
The D Flip-Flop: Edge-Triggered Memory in Digital Design
TL;DR: A D flip-flop captures whatever is on its data (D) input at the moment of an active clock edge and holds that value until the next active edge. Its...
Tag
metastability
A collection of 2 posts
timing-analysis
Setup, Hold, and Metastability in Digital Circuits
TL;DR: Every flip-flop has a setup time () before the clock edge and a hold time () after it during which the data input must remain stable. Violating these constraints...