sequential-logic
Mastering Sequential Logic: The D Latch Explained and Simulated
TL;DR: A D latch stores one bit. It has two inputs (Data and Enable) and follows the characteristic equation . When Enable is HIGH, the latch is transparent — Q...
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sr-latch
A collection of 3 posts
sequential-logic
SR vs. JK Flip-Flops: The Basics of Sequential Logic
TL;DR: The SR latch is the simplest memory element but has a forbidden state when both inputs are 1. The JK flip-flop fixes this by redefining J=K=1 as a toggle,...
sr-latch
The SR Latch: The Simplest Digital Memory Element
TL;DR: The SR (Set-Reset) latch is a bistable circuit built from two cross-coupled NOR gates (active-high) or two cross-coupled NAND gates (active-low). It supports Set, Reset, and Hold operations but...