Mastering Sequential Logic: The D Latch Explained and Simulated
TL;DR: A D latch stores one bit. It has two inputs (Data and Enable) and follows the characteristic equation . When Enable is HIGH, the latch is transparent — Q...
TL;DR: A D latch stores one bit. It has two inputs (Data and Enable) and follows the characteristic equation . When Enable is HIGH, the latch is transparent — Q...
TL;DR: A multiplexer (MUX) selects one of data inputs and routes it to a single output, controlled by select lines. The Boolean expression for a 4-to-1 MUX is . A...
TL;DR: The SR latch is the simplest memory element but has a forbidden state when both inputs are 1. The JK flip-flop fixes this by redefining J=K=1 as a toggle,...
TL;DR: An AND gate outputs 1 only when every input is 1; otherwise the output is 0. Boolean expression . Despite the simple logic, real AND gates have non-zero propagation...
TL;DR: A clock signal is a periodic square wave (typically 50% duty cycle) that synchronizes every flip-flop and pipeline stage in a synchronous digital system. Modern CPUs derive multi-GHz clocks...
TL;DR: A D flip-flop captures whatever is on its data (D) input at the moment of an active clock edge and holds that value until the next active edge. Its...
TL;DR: Browser-based circuit simulators teach digital-logic concepts faster and more reliably than physical breadboards by collapsing the build-test-revise cycle from minutes to seconds, exposing every signal at every node, and...
TL;DR: A half adder sums two single bits to produce Sum (XOR) and Carry (AND). A full adder sums three bits — A, B, and a carry-in — and is...
TL;DR: A half adder is the simplest binary-addition circuit. Two inputs (A, B) produce two outputs: Sum = (XOR) and Carry = (AND). It's only "half" an adder because it...
TL;DR: The NOT gate (inverter) takes a single input and outputs its logical complement: . It is the third member of the AND/OR/NOT functionally complete set. Beyond simple inversion, NOT...
TL;DR: The JK flip-flop is the most versatile 1-bit memory element. Its J and K inputs at the active clock edge select one of four modes — hold (00), reset...
TL;DR: A Johnson counter is a synchronous shift register where the inverted output of the last stage feeds back to the first stage. With flip-flops it produces unique states, and...