The NAND Gate: The Single Building Block of All Digital Logic
TL;DR: A NAND gate outputs 1 unless all inputs are 1 (). It is functionally complete — every other Boolean function can be implemented with NAND gates alone. In CMOS...
TL;DR: A NAND gate outputs 1 unless all inputs are 1 (). It is functionally complete — every other Boolean function can be implemented with NAND gates alone. In CMOS...
TL;DR: An OR gate produces a HIGH output when any one (or more) of its inputs is HIGH. Boolean expression . Where the AND gate demands unanimous consent, OR follows...
TL;DR: A T flip-flop toggles its stored bit on every active clock edge when T=1 and holds it when T=0. Its characteristic equation is . Tied permanently to T=1, it...
TL;DR: Every flip-flop has a setup time () before the clock edge and a hold time () after it during which the data input must remain stable. Violating these constraints...
TL;DR: A buffer outputs — logically a no-op — yet without it, complex digital systems cannot function. Buffers regenerate signal strength to satisfy fan-out limits, distribute clock signals through balanced...
TL;DR: The XNOR gate (Exclusive-NOR) outputs 1 only when its inputs are equal — both 0 or both 1. Boolean expression . Multi-input XNOR chains act as even-parity detectors, and...
TL;DR: The XOR (Exclusive OR) gate outputs 1 only when its inputs differ. Boolean expression . XOR is binary addition modulo 2, the sum bit of a half adder, the...
TL;DR: A Karnaugh map (K-map) arranges a truth table into a Gray-coded 2D grid where adjacent cells differ by one variable. Grouping adjacent 1s into rectangular powers-of-two produces minimal Sum-of-Products...
TL;DR: XOR outputs 1 when inputs differ; XNOR outputs 1 when they match. Multi-input XOR chains detect odd parity; multi-input XNOR chains detect even parity. The choice between them depends...
TL;DR: This tutorial walks through three starter circuits in DigiSim.io: a switch-driven light (digital signals), a 2-input AND gate (logic gates and truth tables), and a multi-gate alarm system (combining...
TL;DR: A 4-bit ripple carry adder chains four full adders so each stage's carry-out feeds the next stage's carry-in. The architecture is simple but slow: total propagation delay scales linearly...
TL;DR: A shift register is a chain of D flip-flops where the output of each stage feeds the input of the next. On every clock edge, every bit shifts one...